1. Field of the Invention
The invention relates to a semiconductor device having a seal ring surrounding a chip region and a manufacturing method thereof.
2. Background Art
A semiconductor device is commonly manufactured by arranging a multiplicity of ICs (integrated circuits), each formed by a plurality of elements and having a prescribed function, in a matrix pattern on a semiconductor wafer such as silicon.
A multiplicity of chip regions on a wafer are separated from each other by a grid-like scribe region (a grid-like scribe line). After a multiplicity of chip regions are formed on a wafer by a semiconductor manufacturing process, the wafer is diced into individual chips along the scribe region, whereby semiconductor devices are formed.
When the wafer is diced into individual chips, chip regions near the scribe line may be subjected to mechanical impact, and the diced cross sections of the separated chips, that is, the separated semiconductor devices, may be partially cracked or chipped.
In order to solve this problem, Patent document 1 proposes a technology of providing a seal ring, a ring-shaped protective wall, in the periphery of each chip region to prevent cracks from spreading in the chip region in a dicing process.
FIG. 22 shows a cross-sectional structure of a conventional semiconductor device having a seal ring (a semiconductor device formed in a wafer).
As shown in FIG. 22, a substrate 1 of a wafer has chip regions 2 divided by a scribe region 3. A layered structure of a plurality of interlayer insulating films 5 through 10 is formed on the substrate 1. An active layer 20 that forms an element is formed in the chip region 2 of the substrate 1. A plug (via) 21 connecting to the active region 20 is formed in the interlayer insulating film 5. A wiring 22 connecting to the plug 21 is formed in the interlayer insulating film 6. A plug 23 connecting to the wiring 22 is formed in the interlayer insulating film 7. A wiring 24 connecting to the plug 23 is formed in the interlayer insulating film 8. A plug 25 connecting to the wiring 24 is formed in the interlayer insulating film 9. A wiring 26 connecting to the plug 25 is formed in the interlayer insulating film 10.
As shown in FIG. 22, a seal ring 4 is formed in the layered structure of the plurality of interlayer insulating films 5 through 10 in the periphery of the chip region 2. The seal ring 4 extends through the layered structure and continuously surrounds the chip region 2. As shown in, for example, Patent document 1, the seal ring 4 is formed by alternately forming a wiring formation mask and a via formation mask. More specifically, the seal ring 4 are formed by an electrically conductive layer 30, a seal via 31, a seal wiring 32, a seal via 33, a seal wiring 34, a seal via 35, and a seal wiring 36. The electrically conductive layer 30 is formed in the substrate 1. The seal via 31 is formed in the interlayer insulating film 5 and connects to the electrically conductive layer 30. The seal wiring 32 is formed in the interlayer insulating film 6 and connects to the seal via 31. The seal via 33 is formed in the interlayer insulating film 7 and connects to the seal wiring 32. The seal wiring 34 is formed in the interlayer insulating film 8 and connects to the seal via 33. The seal via 35 is formed in the interlayer insulating film 9 and connects to the seal wiring 34. The seal wiring 36 is formed in the interlayer insulating film 10 and connects to the seal via 35. A portion of the seal ring which is formed by a wiring formation mask is herein referred to as a seal wiring, and a portion of the seal ring which is formed by a via formation mask is herein referred to as a seal via.
As shown in FIG. 22, a passivation film 11 is formed on the layered structure of the interlayer insulating films 5 through 10 having the wirings (22, 24, 26), the vias (21, 23, 25), and the seal ring 4 formed therein. The passivation film 11 has an opening on the wiring 26. A pad 27 connecting to the wiring 26 is formed in the opening. The passivation film 11 has another opening on the seal wiring 36. A cap layer 57 connecting to the seal wiring 36 is formed in this opening.    Patent document 1: Japanese Laid-Open Patent Publication No. 2005-167198